Design Engineer
Hardware IP design across peripheral interfaces, timing, and communication.
Bio
I design and verify hardware IP for ASIC and SoC, bringing hands-on expertise in RTL design, peripheral interfaces, and SystemVerilog/UVM-based verification.
Experience
Design experience supported by a foundation in verification, simulation, and debugging.
Associate Verification Engineer
RTL design and verification services, verification plans, SV/UVM testbenches, functional tests, coverage analysis, AHB VIP, and USB 2.0 verification environments.
Programming Languages
Verilog · SystemVerilog · UVM · Python · C/C++
EDA tools
Synopsys VCS / Verdi · Synopsys Design Compiler · QuestaSim · Xilinx/Vivado
Education
B.S. Electrical Engineering
Capital University of Science and Technology (CUST), Islamabad
2018–2022Design Projects
QEI / IP design
Quadrature Encoder Interface
Worked on quadrature encoder interface IP for motion feedback using encoder signals.
QEIMotion feedback
IP design
Input Capture
Worked on input capture IP for capturing signal events used in timing and measurement.
Input captureEvent timing
IP design
I²C
Worked on I²C communication IP for serial connectivity between peripherals.
I²CSerial communication
PLL / IP design
Phase-Locked Loop
Worked on PLL IP for clocking applications.
PLLClocking
IP design
CAN 2.0
Worked on CAN 2.0 communication IP for Controller Area Network interfaces.
CAN 2.0Communication
IP design
SPI
Worked on SPI IP for synchronous serial communication with peripherals.
SPISerial communication
Verification Projects
Public repository
UART
A programmable UART with an APB register interface and a UVM learning environment. Includes a register model, architectural scoreboard, functional coverage, and directed/random tests.
VerilogSystemVerilogUVMAPB / RAL
Explore repository Learning / reference implementationVerification
USB 2.0
Verification planning, an SV/UVM environment, functional tests, and a scalable scoreboard comparing observed outputs against predicted data.
SystemVerilogUVMUSB 2.0
Professional projectVerification IP
AHB
A UVM-based AHB VIP supporting non-sequential, non-pipelined transfers and 8-, 16-, and 32-bit read/write transactions.
AHBUVMSystemVerilog
Professional projectAcademic Project
Final-year project
Self-driving car prototype
A prototype using deep neural networks and computer vision to detect lane lines and traffic signs.
PythonComputer visionDeep learning
2021–2022 · Academic projectLet’s build something
that works.
For opportunities and conversations about hardware design and verification.